Introducing

Apitronix Cerebellum

Next-generation multicore RISC-V SoC

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Overview

The Cerebellum at a glance

RISC-V CPU

  • 4.25 CoreMark/MHz
  • Core-local memory — no shared cache
  • Heterogeneous allocation (e.g. dedicated crypto cores)
  • 220 independent cores

MessagePrism

  • Inter-core messaging fabric
  • True real-time determinism
  • Hardware-enforced security contracts

ML Acceleration

  • Per-core FP8 acceleration
  • ~HBM3 memory bandwidth

Software Defined Peripherals

  • Ethernet, CAN, CAN-FD, Timers & more
  • Hardware accelerated
  • Event timing & routing

The Deterministic Advantage

  • No cache — no hidden latency
  • Interrupts pinned to individual cores
  • Deterministic inter-core messaging
  • True Freedom From Interference (FFI)
  • WCETs straightforward to calculate

Contact the Apitronix team to learn more about the Cerebellum family.